1. Field of the Invention
The present invention relates to computer memory, and in particular, to a hidden refresh 2P2N pseudo SRAM (static random access memory) and its hidden refresh method.
2. Description of the Related Art
Memory plays an indispensable role in computer industries. Usually, a memory is classified into a DRAM (dynamic random access memory) and a SRAM (static random access memory) according it's respective data storage capability. DRAM is advantageous for its small size, but requires periodic refresh to prevent data loss due to current leakage. SRAM is advantageous for its simple operations, but occupies a large chip area.
FIG. 1A (Prior Art) is a circuit diagram showing a conventional 1T1C memory cell of a DRAM. As shown in FIG. 1A, the 1T1C memory cell, known in the art, includes an access transistor T1 and a storage capacitor CS. The access transistor T1 has a source connected to the storage capacitor CS, a gate connected to a word line WL, and a drain connected to a bit line BL. FIG. 1B (Prior Art) is a diagram showing the 1T1C memory cell in FIG. 1A formed on a semiconductor substrate. As shown in FIG. 1B, a parasitic diode D1 (PN junction) is formed between the source of the access transistor T1 and the storage capacitor CS. Therefore, a logic "1" signal stored at the storage capacitor CS gradually decays even when the access transistor T1 is shut off, where the word line WL is "0". To prevent data loss, periodic refresh is performed for the DRAM, which reads the logic "1" signal stored at the storage capacitor CS, amplifies the logic "1" signal by a sense amplifier (not shown) connected to the bit line BL, and writes back the amplified signal.
FIG. 2 (Prior Art) is a circuit diagram showing a conventional 3T memory cell of a DRAM As shown in FIG. 2, the 3T memory cell, known in the art, includes a read transistor T2, a storage transistor T3, and a write transistor T4. The read transistor T2 has a gate connected to a read word line RWL, a drain connected to a read bit line RBL, and a source. The storage capacitor T3 has a gate, a drain connected to the source of the source of the read transistor T2, and a source connected to a negative source voltage of the DRAM. The write transistor T4 has a gate connected to a write word line WWL, a drain connected to the word bit line WBL, and a source connected to the gate of the storage transistor T3. As in the 1T1C memory cell in FIGS. 1A and 1B, a logic "1" signal stored at the storage transistor T3 decays due to a leakage current. To prevent data loss, periodic refresh is performed for the DRAM, which reads the logic "1" signal stored at the storage transistor T3 through the read word line RWL, amplifies the logic "1" signal by a sense amplifier (not shown) connected to the bit line BL, and writes back the amplified signal through the write word line WWL.
FIG. 3 (Prior Art) is a circuit diagram showing a conventional 4T memory cell of a DRAM. As shown in FIG. 3, the 4T memory cell, known in the art, includes four NMOS transistors N1, N2, N3 and N4. The NMOS transistors N1 and N2 have their sources connected to a negative source voltage, and gates and sources cross coupled to each other to form a cross-couple latch storing a pair of signals S/S'. The NMOS transistors N3 and N4 have their gates connected to the word line WL, and drains and sources connected to a pair of bit lines BL/BL' and the drains of the NMOS transistors N1 and N2, respectively, to access the pair of signals S/S' stored at the cross-couple latch. The storage data swing of the pair of signals S/S' is a positive source voltage of the DRAM minus a threshold voltage (VDD-VTN) of the NMOS transistors N1, N2, N3 and N4. When the NMOS transistors N3 and N4 are closed (i.e., the word line WL is "0") and the pair of signals S/S' at the cross-couple latch are "0"/"1"(VDD-VTN), the signal S is not floating, whereas the signal S' is floating. Therefore, as in the 1T1C memory cell in FIGS. 1A and 1B, periodic refresh is performed to prevent data loss at the signal S', which only opens the word line WL for a short time to ensure that load L connected to the pair of bit lines BL/BL' provides sufficient refresh currents. The load L can be controlled to function only when performing pre-charging and refresh operations of the DRAM, thereby reducing the power consumed.
Compared with the 1T1C memory cell which is manufactured using a stack process or a trench process, the 4T memory cell is manufactured using a standard CMOS process, known in the art. Further, the 4T memory cell stores data differentially (such as the pair of signals S/S') and has a larger noise margin and a higher access speed. Therefore, most pseudo RAMs are structured with 4T memory cells to be manufactured using a standard CMOS process.
FIGS. 4A and 4B (Prior Art) are circuit diagrams showing a 6T memory cell of a SRAM, known in the art. To prevent floating of the differential signals S/S' in the 4T memory cell of FIG. 3, two PMOS transistors P1 and P2 are included in the 4T memory cell to obtain a SRAM cell which operates as the 4T memory cell, as shown in FIG. 4A. The PMOS transistors P1 and P2 have their sources connected to a positive source voltage of the SRAM, gates connected to the drains of the NMOS transistors N2 and N1, and drains connected to the drains of the NMOS transistors N1 and N2, respectively. Further, the access NMOS transistors N3 and N4 in FIG. 4A can also be replaced with two PMOS transistors P3 and P4, as shown in FIG. 4B. In this case, the PMOS transistors P1 and P2 constitute a cross-couple latch, and the NMOS transistors N1 and N2 are provided only to prevent floating of the differential signals S/S'.
Further, since the leakage current is mostly derived from reverse bias leakage of the parasitic diode, the PMOS transistors P1 and P2 can be also replaced with two resistors R1 and R2 (10.sup.10.about.10.sup.11.OMEGA.), as shown in FIG. 4C (Prior Art), that provide a supply current which is larger than the leakage current and prevent data loss of the differential signals S/S'. In this case, the resistors R1 and R2 can be formed above the NMOS transistors and occupy the same chip area as the 4T memory cell. Further, the resistors R1 and R2 in FIG. 4C can be replaced with two thin film transistors TFT1 and TFT2 to obtain a larger noise margin and a lower standby current, as shown in FIG. 4D (Prior Art). In this case, the thin film transistors TFT1 and TFT2 can also be formed above the NMOS transistors and occupy the same chip area as the 4T memory cell.
From the above, a pseudo SRAM with 4T memory cells can be manufactured using a standard CMOS process, reducing chip area by two PMOS transistors, and operate as a standard SRAM. However, it is also necessary to include a refresh operation (that is, opening all word lines for a short time) except normal read/write operations, which result in power loss.
FIG. 5A (Prior Art) is a circuit diagram showing a driver of a conventional pseudo SRAM. As shown in FIG. 5A, the driver of the memory array 10 includes a row address decoder 11, a column address decoder 12, a multiplexor 13, a refresh counter 14, and a controller 15. The multiplexor 13, under the control of the controller 15, selectively transfers a row address RA or a counting result of the refresh counter 14 to the row address decoder 11 to generate a driving signal of a corresponding word line of the memory array 10. The column address decoder 12 receives a column address CA to generate a driving signal of a corresponding bit line of the memory array 10. Therefore, access and refresh operations of the memory array 10 can be performed according to the driving signals generated by the row address decoder 11 and the column address decoder 12.
The refresh counter 14 in FIG. 5A can be replaced with a shift register 16, as shown in FIG. 5B (Prior Art). In this case, the shift register 16 sequentially outputs a pulse to serve as a driving signal of a corresponding word line of the memory array 10. Meanwhile, the row address decoder 11 also receives a row address RA to generate a driving signal of the corresponding word line. The multiplexor 13 then selectively transfers the driving signal of the row address decoder 11 or the shift register 16 to drive the corresponding word line. The column address decoder 12 receives a column address CA to generate a driving signal of a corresponding bit line of the memory array 10. Therefore, access and refresh operations of the memory array 10 can be performed according to the driving signals which are respectively selected by the multiplexor 13 and generated by the column address decoder 12. FIG. 5C (Prior Art) is a circuit diagram showing the shift register 16 in FIG. 5B. As shown in FIG. 5B, the shift register 16 is structured with D flip flops which are connected in a ring and controlled by a system clock CLK. When a pulse is input to the shift register 16, the pulse will propagate along the D flip flops at the rising edge or the falling edge of the system clock CLK. Therefore, if the number of the D flip flops is designed to be the same as the number of the word lines of the memory array 10, the output of the shift register 16 can be directly used as driving signals for the word lines of the memory array 10.
In the pseudo SRAM with 4T memory cells, when the access transistors N3 and N4 are closed (i.e., the word line WL is "0"), the transistor N1 (or N2) which stores a logic "1" signal can be refreshed not only by changing the voltage levels of the pair of bit lines BL/BL', but also by opening the word line WL. Further, when the access transistors N3 and N4 are open (i.e., the word line WL is "1"), a large read current will flow into the transistor N2 (or N1) which stores a logic "0" signal, thereby causing data confusion when simultaneously opening two or more word lines. Therefore, the pseudo SRAM must be refreshed by row which consumes extra power.
Accordingly, there is a general need in the art for an improved, optimized SRAM for use in a computer. In particular, there is a need to provide a hidden refresh 2P2N pseudo SRAM, which avoids data confusion when opening plural word lines at the same time and reduce power consumption.